Task Description
This task requires the design, simulation and physical implementation of a 4-bit ALU using the hardware description language Verilog with the finished design implemented upon an Altera DE2-115 FPGA development board.
The envisaged design will be hierarchical, with some design elements provided direct from class notes, whilst others require modification and/or complete design.
To complete this task you will need to use Altera Quartus that is freely available to download (web pack version).
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