Circuit Analysis and Design

 

Microelectronics – Circuit Analysis and Design

Cascade Amplifier Design

 

1. Introduction

The ECE318 class requires the students to conduct a project related to materials learned during the semester.  This semester’s project requires each group to design and simulate a cascade amplifier using BJTs. The cascade amplifier should attain required gain for a specified load. All design specifications are given in section II. Each group needs to submit a final report following the requirement introduced in section IV.

1. System Block Diagram and Required Specifications

A properly functioning amplifier circuit consists of amplification stage followed by output stage, as shown in Figuire 1. In the amplification stage, single CE circuit generally cannot provide enough gain. Thus, cascade design (two CEs) is required to attain required gain. Also, due to the Loading Effect, the small resistance load can not occupy all of the output voltage. Thus, a output stage CC circuit, which has low output impedance, is required before feeding the load. The available components are constrained as below which must be followed.

Circuit input: V = 10mV peak, 2k Hz AC;

Circuit load: R = 10Ω;

Circuit gain (with load): 6 < Av < 10;

DC supplies: V_CC = 9V DC; V_EE = 0V DC;

Transistors: BJT (2N2222A);

Transistor parameters: β = 209; V_T = 26 mV; V_A = ∞;

Resistors: All values are available;

Capacitors: 0.2uF;

 

 

Figure 1 Amplifier circuit block diagram

 

 

• Design Procedure

 

The amplifier should be designed by hand calculation and simulated by Multisim to be verified and tuned. Some important design hints are given by the end of this section.

 

A general procedure is introduced as following:

Step 1: Design 1st CE circuit to meet the required Q₁point in Figure 2.

Step 2: Model and simulate the design of Step 1 with and without load.

Step 3: Design 2nd CE circuit to meet the required Q₂ point in Figure 2.

Step 4: Connect 1^st and 2^nd CEs to have a cascade amplifier as shown in Figure 3. Model and simulate the cascade circuit with and without load.

Step 5: Design output stage CC circuit as shown in Figure 4, to have as large gain as possible. (DC component of cascade circuit output should be equal to the biasing (DC) base voltage of CC.)

Step 6: Connect the cascade circuit and CC circuit. Model and simulate the design with and without load.

Step 7: Tune your design (if necessary) to have a nice sinusoidal output voltage and meeting all specifications in section II.

 

 

 

 

 

 

 

Design Hint:

• R1, R2, R3 and R4 should be big;
• RC1, RE1, RC2 and RE2 should be small;
• RC’s should be multiple times of RE’s.

 

 

1. Final Report Requirements

 

1. Report questions and requirements:
2. (5 pts) Show detailed design calculation in DC analysis of Step 1.
3. (5 pts) Show detailed AC analysis (find A_VO) of designed circuits in Step 1.
4. (3 pts) Show screenshot of simulation circuits of Step 6.
5. (5 pts) Show screenshot of simulation multimeter readings of V_CE and I_C of two CE circuits of Step 4.
6. (6 pts) Show simulation oscilloscope waveforms of output voltage (with load) in Step 2, Step 4 and Step 6.What is the gain value?
7. (6 pts) Show simulation oscilloscope waveforms of output voltage (without load) in Step 2, Step 4 and Step 6.What is the gain value?

 

2. Report format:

Your final report should at least include followings:

Cover page (5 pts)– Project name, semester, course title/number, student name, submission date

Introduction (20 pts) – Description of this project objectives and outcomes

Design procedure (55 pts) – Description of “what you have done” (25 pts) andpresentation of answers of IV.1 (30 pts).

Conclusion (20 pts) – Discussion and comments on the overall project outcomes

 

 

Note:  This is a project for DESIGN and thus there does NOT exist a standard key.